Interface Specifications

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Instruction Set:

Operation Code
Dec(Hex)

01(01)    CLRRA (clear register A)
02(02)   CLRRB  (clear register B)
03 (03)   CLRACC  (clear Accumulator)
04 (04)   LDRA (immediate, load register A)
05 (05)   LDRA (direct, load register A)
06 (06)   LDRB (immediate, load register B)
07 (07)   LDRB (direct, load register B)
08 (08)   DECRA (decrement registry A)
09 (09)   DECRB  (decrement registry B)
10 (0A)  DECACC (decrement accumulator)
11 (0B)  INCRA (increment registry A)
12 (0C)  INCRB (increment registry B)
13 (0D)  INCRACC (increment accumulator)
14 (0E)  STRA (direct, store Register A)
15 (0F)  STRB (direct, store Register B)
16 (10)  STACC (direct, store accumulator)
17 (11)  ADD (add register B to register A and store results in accumulator) 
18 (12)  JMP () ( immediate, jump unconditionally (load PC) immediate Mode). 
19  (13) JMP(>) (immediate, JMP if comparator greater than output true.)
20  (14) JMP(=) (JMP if comparator equal output true)
21  (15) JMP(<) (JMP if comparator less than output is true)
    
 Notes:

1. Immediate Mode: Operation is performed on address immediately following operation code.   

2. Direct Mode: Address immediately following operation code contains address of  operand.

3. Implied Mode: Operand is implied by operation code. Example: Code 01, CLRRA operates on register RA.

4. Only three arithmetic functions are performed by this computer. 
    a. Count (up or down)
    b. Addition
    c. Comparison

 5. This programmers model of computer only shows registers, Buses, and an Accumulator to show result of addition, and bit indicators (< =  >) to show results of comparison. 

6.  Negative numbers or 2's compliment arithmetic is not supported.

7.  Burn Proms : Simulates the burning of the program you wrote into a uvProm. Actually it causes the data in the text boxes to be written into an array (JAVA script).  

8.  Load RAM : Simulates loading data into 16 byte Random Access Memory. Naturally you cannot type data directly into memory. But the I/O for writing data into memory is beyond the scope of this introduction to computers.

9.  Single Step: Causes program to advance through one completes operation. At end of cycle program counter will point to next instruction. All remaining register contents are whatever was in register at end of the cycle. Data Bus and Address Bus reflect last valid data and address of previous instruction cycle.

10. I express all numbers as decimal.  The numbers are really binary in simulation metaphor and in JAVA program.  The numbers could also be represented as octal or hexadecimal. The numbers cannot be represented as Binary Coded Decimal (BCD). You will have to convert decimal numbers to binary in order to relate them to voltage readings on P1.

11.  Most of the voltages that can be read are dynamic and therefore need to be read at a single point in time. The point of time I used is the last CS  ( Chip Select ) of the single step cycle. Chip select goes high after address valid and before address invalid. This could be achieved in reality by sampling voltage with a sample and hold circuit and connecting output to voltmeter.  The sample control gate would always be connected to CS ( Chip Select ).  Of course this same information could easily be obtained using two channels of an oscilloscope; using one probe on CS and the other on the test points.  Unfortunately, to the best of my knowledge their are no browsers with X/Y plot capabilities.    I 

12. Switches are read at address 241 when R/W(not) = high.  LED data is latched at address 241 when R/W(not) = low. 

13. Chip Select (P1-11) will always appear high since sampling of all test points is controled by Chip Select.